System and method of mapping an array to processing elements
US5659778A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1994 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Apr 11, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for efficiently mapping elements of an array to processing elements (PEs) of a parallel data computer. Axis lengths and weights are received from a compiler (if invoked at compile time) or an application program (if invoked at run time). A physical grid is generated by expanding the axis lengths so that their product is integrally divisible by "machine.sub.-- bits" (i.e., log.sub.2 (number of PEs on the data parallel computer)). The physical grid is divided into subgrids of equal size by dividing each expanded axis length into subgrid lengths of equal length. The lengths and numbers of subgrid lengths in each axis are then output to the compiler or the application program. From the subgrid lengths, the compiler or application program can identify a unique location in one of the subgrids given any location of an element in the array. From the number of subgrids in each axis, the compiler or application program can identify a unique memory location on a unique PE given the subgrid and location identified from the subgrid length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.