Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU
US5659789A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1995 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Dec 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a fault tolerant system for providing power to a multiple central processing unit computer system. Three DC-DC converters, each sized for providing power to one central processing unit, furnish power to two central processing units through two power planes. Each DC-DC converter has an output voltage level selectable through a voltage identification signal. If the voltage identification signals of the converters match, identification logic couples the power planes together. If only one converter is available to power the two central processing units, a stopclock logic circuit alternatively places the central processing units in known stopclock modes. Thus, the single converter only has to fully power one central processing unit at any one time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.