Method for via formation with reduced contact resistance
US5661083A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1996 |
| Grant date | Aug 26, 1997 |
| Priority date | — |
| Expiry date | Jan 30, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a via in an integrated circuit having a reduced contact resistance. The integrated circuit includes a photoresist layer, an oxide layer, an etch stop layer and a metal layer. In one embodiment, a portion of the photoresist layer is removed to expose the underlying oxide layer, after which a portion of the oxide layer is removed to expose the underlying etch stop layer. A portion of the etch stop layer is then removed using a reactive ion etch-downstream microwave ash system under conditions that are effective to create a substantially water-soluble polymer residue within the via, to expose a portion of the underlying metal layer. The water-soluble polymer is then removed to expose the underlying metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.