On-chip positive and negative high voltage wordline x-decoding for EPROM/FLASH
US5661683A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 1996 |
| Grant date | Aug 26, 1997 |
| Priority date | — |
| Expiry date | Feb 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An on-chip positive and negative high voltage wordline x-decoding system for EPROM/FLASH is disclosed wherein three transistors are required for each wordline. The x-decoding system minimizes system latch-up by separating the positive and negative high voltage portions of the system. The high-voltage portion of the x-decoding system includes a native mode PMOS transistor fabricated in a N-well on a common P-substrate and a high-voltage NAND gate that supplies a control signal to the gate of the PMOS transistor. In response to a variable power signal (which is at O VDC in erase mode, VCC in a read mode, and approximately +10 VDC in program mode) and the control signal (which is low when the memory cell is selected and the system is in read or program modes), the positive portion pulls the selected word line up to VCC and +10 VDC in read and program modes, respectively. The negative voltage portion of the system includes two NMOS transistors fabricated in a P-well within a separate N-well on the common P-substrate. Together, the NMOS transistors pull an unselected word line down to 0 VDC in program/write mode, to 0 VDC in read mode, and pull a selected word line down to -9 VDC in era…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.