Semiconductor memory having built-in self-test circuit
US5661729A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1996 |
| Grant date | Aug 26, 1997 |
| Priority date | — |
| Expiry date | Apr 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test pattern generation circuit is stored in a semiconductor memory, a writing operation is carried out with an address sequence pattern and a test data pattern generated with a clock signal obtained from an external part during a test mode, the test data pattern and the read-out data are compared from each other during a reading-out operation, a pass or non-pass discrimination signal in the memory is attained in response to whether both of them are coincided with each other or not, the pass or non-pass discrimination signal is outputted to an external terminal, the number of test signal driving signals is reduced and the number of parallel test chips is increased so as to reduce a test cost. In addition, the memory has a power supply shut-off control circuit and a stable test is carried out by shutting-off the power supply in the case that the power supply shows a short-circuited state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.