Method for fault correction in a power converter circuit arrangement
US5663858A · kind A · utility
5Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 30, 1995 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Aug 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/325
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for fault correction in a power converter circuit arrangement. The power converter circuit arrangement has a plurality of switch modules which consist, for their part, of a parallel circuit of semiconductor chips. The semiconductor chips are interconnected via connecting wires, preferably bonding wires. If, because of a defect, a chip forms a short circuit, the connecting wires of chip are severed by specific current pulses. The advantage resides in that a short circuit of an individual chip does not put the entire circuit arrangement out of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.