Checksum generation circuit and method
US5663952A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 7, 1995 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Jul 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit and method for generating a checksum for a TCP packet on the fly. A stream of 32-bit data words from a TCP packet is split into two 16-bit data word streams and separately summed using 16-bit adders. The carry-out from the adders is tied to the carry-in thereof so as to incorporate any carry bits generated into the sum. At the end of the data stream, three further summing cycles are used in order to generate the final 16-bit one's complement checksum. First, the two 16-bit data stream partial sums are added together, including any carry bit from one of the adders while the carry-out from the other adder is stored. In the second cycle the stored carry-out and the carry-out from the first cycle are added into the sum. In the third cycle, any carry bit generated in the second cycle is added to the sum so as to produce the final checksum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.