Integrated circuit chip having built-in self measurement for PLL jitter and phase error

US5663991A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ram Kelkar · South Burlington, US
• Ilya I. Novof · South Burlington, US
• Stephen D. Wyatt · Jericho, US

Key dates

• Filing date: Mar 8, 1996
• Grant date: Sep 2, 1997
• Expiry date: Mar 8, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/0812
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A built-in system and method is provided that measures Phase Lock Loop (PLL) output clock error. An edge sorting circuit is utilized to measure jitter between corresponding transition edges of a measured clock and a reference clock, and then stores the value in an N bit word. A decoder circuit reads in the value and increments a corresponding counter. A state machine then reads the counters, processes the information and outputs one or more PLL clock error values.