Transfer processor including a plurality of failure display units wherein a transfer process is prohibited if failure is indicated in a failure display unit
US5664104A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1993 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Dec 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.