Method and apparatus in a data processing system for selectively inserting bus cycle idle time
US5664168A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1996 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Feb 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/376
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus in a data processing system (10) for selectively inserting bus cycle idle time. The present invention allows a data processing system (10) to selectively insert a predetermined number of idle clocks at the end of a bus cycle. In one embodiment of the present invention, there is a base register (48) and an option register (46) corresponding to each one of the chip select terminals (73). In one embodiment of the present invention, each option register (46) includes a user programmable idle control bit (110). If a first chip select is used to select a peripheral device during a bus cycle to that same peripheral device, the idle control bit (110) which corresponds to the first chip select determines whether or not one or more idle clocks will be inserted after that bus cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.