Silicon etching method
US5665203A · kind A · utility
85Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1995 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Apr 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching silicon is described incorporating first and second steps of reactive ion etching through a patterned oxide layer in respective atmospheres of HBr, Cl.sub.2 and O.sub.2 and then HBr and O.sub.2 in situ by terminating the first etching step and removing substantially all Cl.sub.2 before continuing with the second step of etching. The invention overcomes the problem of uneven etching of n+ and p+ silicon gates for CMOS transistor logic during the step of simultaneously etching silicon to form sub 0.25 micron gate lengths and vertical sidewalls while stopping on the gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.