Device having current ballasting and busing over active area using a multi-level conductor process
US5665991A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 1995 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | May 31, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.