Binary relative delay line
US5666079A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 6, 1994 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | May 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0037
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A binary relative delay line device having two delay lines, each of which delays, during a time interval, an input signal by a substantially equal amount of time. Each delay line requires a settling time before it is selected during a next time interval. A selection and delay determining circuit is coupled to the two delay lines to select one of them to provide an output signal. A clock is coupled to the selection and delay determining circuit to operate the selection and delay determining circuit at a lower frequency than the frequency of the input signal, the lower frequency being chosen so that any selected delay line has settled before it is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.