Current memory
US5666303A · kind A · utility
11Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1996 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Aug 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A current memory for balanced current inputs comprises two coarse and two fine current memory cells each of which comprises a field effect transistor having a switch between its gate and source electrodes. Parasitic gate-drain capacitances are neutralised by capacitors connected between the gate and drain electrodes of opposite pairs of transistors. Other current transport errors can be compensated by providing appropriately dimensioned extra capacitance added to each of the neutralising capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.