Phase-locked loop timing controller in an integrated circuit memory
US5666322A · kind A · utility
153Cited by
5References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 21, 1995 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Sep 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Interleaved operation of multiple memory banks is improved by including a frequency multiplier and a synchronizing circuit, such as a phase-locked loop, as part of an integrated circuit memory chip. Frequency multiplication supplies additional clock edges for timing different phases of the system clock signal. The synchronizing circuit provide precise control of clock edge timing to exactly align the timing signals in one memory chip with the timing signals in another memory chip despite variability in temperature, process and voltage parameters between the chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.