Digital demodulating apparatus capable of selecting proper sampling clock for data transmission speed
US5666386A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 1996 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Oct 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a digital data demodulating apparatus, total number of low-pass filters is reduced by supplying variable sampling clock signals to A/D converters coupled to the low-pass filters. The digital data demodulating apparatus for receiving/demodulating a transmission signal that is modulated by digital data in a predetermined modulation manner, includes: a detecting unit for detecting the transmission signal; a low-frequency component passing unit for causing a low-frequency component of the transmission signal detected by the detecting unit to selectively pass therethrough; an analog-to-digital (A/D) converting unit for A/D-converting the output from the low-frequency component passing unit into a digital transmission signal; a demodulating unit for demodulating the digital transmission signal from the A/D converting unit; and a switching unit for switching a frequency of a sampling clock produced from the A/D converting unit in response to an external switching instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.