Four state two bit recoded alignment fault state circuit for microprocessor address misalignment fault generation
US5666508A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for controlling address alignment fault generation employing a recoded two bit structure. This alignment fault state circuit stores one of four states corresponding to whether the operating system permits address misalignment fault generation and whether the application program requests such address misalignment fault generation. The two latches each hold either a first state or a second state. Together the two latches have either a first combined state, a second combined state, a third combined state or a fourth combined state. The two latches have a recoded set of states such that receipt of at least one of the alignment check on instruction, the alignment check off instruction, the alignment mask permit instruction or the alignment mask prohibit instruction causes both latches to change state. An output circuit generates an alignment fault qualifier signal enabling generation of an address alignment fault signal if the two latches has a predetermined one of said first, second, third or fourth combined state. An alignment detector receives an indication of the selected data size and the least significant bits of the generated address which is ANDed with the alignment…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.