Data processing device having an expandable address space
US5666510A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1996 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Jan 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data information has its byte/word size specified by the size bit of an operation code. The utilization of the data information of a long word size is specified by either the prefix code or the operation code to which is newly added the same bit number as that of the low-order CPU. For the data information of the byte size, the high-/low-orders of the byte size register to be utilized are specified by predetermined 1 bit of a register specifying field. For the data information of the word size, the high-/low-orders of the word size register are specified by the predetermined 1 bit of that data information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.