Power down scheme for idle processor components
US5666537A · kind A · utility
71Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1994 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Aug 12, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power down circuitry in a processor for controlling power delivered to functional units of the processor, comprising first and second power down circuits. The first power down circuit comprises a state machine having a decoded instruction as input and a control signal as output. The control signal disables a clock signal to a floating point unit (FPU) when the decoded instruction is not a floating point instruction. The second power down circuit comprises a prediction circuit that generates a predict signal when a cache access cannot occur. The predict signal disables a clock signal to a cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.