Bus maintenance circuit
US5668482A · kind A · utility
9Cited by
8References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 15, 1996 |
| Grant date | Sep 16, 1997 |
| Priority date | — |
| Expiry date | Mar 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A maintenance circuit for a bus (1) with a tristate driver (2) which includes a keeper circuit (3) having a first inverting logic gate (4) with an input connected to the bus (1) and a second inverting logic gate (5) with an input (6) connected to the output of the first logic gate (4). The output of the second logic gate (5) is restricted in current relative to that of tristate driver (2) and is connected directly to the bus (1). The keeper circuit (3) has a control input (7) for disabling positive feedback therein, such that the keeper circuit (3) acts as a pull-up or pull-down circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.