Radix 2 architecture and calibration technique for pipelined analog to digital converters
US5668549A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1994 |
| Grant date | Sep 16, 1997 |
| Priority date | — |
| Expiry date | Nov 10, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a pipelined radix 2 analog to digital converter, a method of analog residue formation uses an overflow reduction stage which takes an analog input and outputs a digital value of +2, 0, or -2 and an analog residue which is twice the analog input minus the digital output value times a reference voltage. A calibration technique allows a pipelined analog to digital converter using the overflow reduction stages to produce a corrected output requiring one addition per pipeline stage. The residue portion of the overflow reduction stage can be constructed using an operational amplifier, two capacitors, one of which has twice the capacitance of the other, and three on-off type switches. A radix 2 pipelined converter is constructed using a combination of standard 1-bit stages and overflow reduction stages. The analog residue is passed from stage to stage as an amplifier remainder as the digital codes are extracted in a pipelined analog to digital converter. The overflow reduction stage reduces out-of-range residues back to in-range residues. Using three digital output values where the difference between any two is greater than one raw output code prevents the possibility of multiple repre…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.