Tiled, flat-panel displays with luminance-correcting capability
US5668569A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1996 |
| Grant date | Sep 16, 1997 |
| Priority date | — |
| Expiry date | Apr 5, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S345/903
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention features a tiled, flat-panel, mosaic display with a luminance-correcting capability and having a seamlessness characteristic. Column and row inputs that are typically provided for a single flat panel are distributed over a number of tiles. The display is fabricated by sorting the tiles into groups, and matching their color coordinates prior to assembly. After assembly, measurements of the luminance of the display are processed to generate correction data, which is compressed into a reduced set of coefficients. A processor, located between a video controller and the display drivers for each of the tiles, has a memory containing these interpolation coefficients for correcting luminance in the tiles. A multiplicity of processing units is connected to the video controller and the processor for performing video correction in real time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.