System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource
US5668949A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1995 |
| Grant date | Sep 16, 1997 |
| Priority date | — |
| Expiry date | Oct 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid decoding module which resides on the computer system's high speed memory bus. The computer system incorporating the hybrid decoding module scheme is capable of having centrally decoded resources on the memory bus as well as resources capable of decoding memory bus addresses directly. During system initialization, or after a hard reset, the decoding logic polls each of the resources on the memory bus to determine whether the resource is a centrally decoded resource or a distributed decode resource. A table is maintained for all centrally decoded resources such that when addresses are put out by the processor during run-time, the decoding logic is capable of directing control to the centrally decoded resource. Another aspect of the present invention is implemented during the initialization of the system. When resources are polled by the decoding logic, they are also provided with an identifier which identifies the last available I/O space slot. If the memory bus resource requires this I/O space for its own use, it signals the decoding module that it should be assigned to that resource.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.