Method of monitoring system bus traffic by a CPU operating with reduced power
US5669003A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1994 |
| Grant date | Sep 16, 1997 |
| Priority date | — |
| Expiry date | Dec 23, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for maintaining cache coherency while minimizing the power consumption. The method includes operating a first processor in a reduced power mode. While the first processor is operating in a reduced power mode, certain portions of the internal logic in the first processor remain clocked so that the first processor continues to monitor transactions on the system bus. The second processor runs a transaction on the system bus to request data. In the event that the first processor determines that the transaction by the second processor is requesting cache data that is stored in the first processor in a modified state, the first processor signals the second processor. After the current bus cycle is completed, the first processor writes back the modified cache line on the system bus and second processor re-runs the transaction on the system bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.