Logic circuit controlled by a plurality of clock signals
US5670899A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 1995 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Nov 9, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control. The CMOS gate is provided with an auxiliary PMOS transistor being inserted at the PMOS transistor side and an auxiliary NMOS transistor being inserted at the NMOS transistor side. A timing control circuit is provided that generates a control clock signal adapted to maintain the auxiliary PMOS transistor and th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.