Programmable digital delay unit
US5670904A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1995 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Sep 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable digital delay unit presenting a number of cascade-connected delay blocks, and a number of controlled bypass elements, one for each delay block. Each bypass element presents a bypass line and a multiplexer for selectively connecting the input or output of the respective delay block to the input of the next delay block. The delay blocks are formed by the cascade connection of flip-flops, and the number of flip-flops in each successive delay block, from the input of the delay unit, decreases in an arithmetic progression to the power of two, so that the selection signals for the respective multiplexers represent the bits of a digital word specifying the required delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.