Display refresh system having reduced memory bandwidth
US5670993A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/39
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display refresh system (10) is disclosed wherein a display image is stored in a screen memory (12) as a number of screen rows (26) having consecutive addressable units. A redundancy memory (38) includes a redundancy row (48) corresponding to each screen row (26). Each redundancy row (48) stores run length data that indicates the number of identical consecutive addressable units within a screen row (26). Addressable units are written with accompanying run lengths to a FIFO (54). A register repeater (56) repeats the addressable unit at the FIFO output (62) a number of times equal to the run length. The run length is used to advance the refresh address to the next group of identical consecutive addressable units within the screen row (26).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.