Method and apparatus for improved video filter processing using efficient pixel register and data organization
US5671020A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 1995 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Oct 12, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/14
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data values. An address decoder receives an address for accessing n data values at a time from the memory modules and asserts address values to access corresponding rows of the first and second memory modules. Select logic selects between respective columns of the first and second memory modules to retrieve the desired data values according to a predetermined order. A shift network reorders the retrieved data values, if necessary, to place them in the proper order for the processing array. The address decoder provides a select value to the select logic and a shift value to the shift network for each cycle. For purposes of horizontal decimation, the pixel values are organized into an even and an odd group, which groups are stored in the memory buffer in two separate regions separated by an address offset K. This data organization maximizes utilization of the processing array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.