Patent · US Expired

Apparatus and method for checking logic circuit

US5671148A · kind A · utility

3Cited by
7References
16Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 27, 1995
Grant dateSep 23, 1997
Priority date—
Expiry dateNov 27, 2015

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/30
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

An apparatus and method for checking logic circuit checks logic element influenced by hot carriers in the logic circuit. The present invention comprises means for measuring rising transition time t.sub.r (or falling transition time t.sub.f) of signal generated by logic element comprising one portion of the logic circuit; means for calculating a ratio (DUTY) of rising transition time t.sub.r (or falling transition time t.sub.f) and operation period T of the signal; and means for comparing said DUTY with maximum allowable duty (DUTYMAX), in order to detect the logic element having DUTY exceeding maximum allowable duty (DUTYMAX).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.