System and method for modelling integrated circuit bridging faults
US5671150A · kind A · utility
7Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1994 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Oct 13, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3173
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for simulating bridging faults uses means for retrieving, as a function of voltage, strengths of simple transistor circuits relative to the strength of a reference device. This relative strength is used to determine the voltage at bridge faults. The bridge voltage is compared to the threshold voltages of devices connected to the bridging node to determine the logic interpretation by such gates of such voltage. Other systems and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.