Self-timed logic circuit having zero-latency overhead and method for designing same
US5671151A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 1994 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Nov 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0966
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Asynchronous combinatorial logic apparatus and method are provided that propagate data through a logic array at the speed of a raw combinational logic array and generate a functional output signal. The apparatus and method provide a minimum expected value of data propagation delay. In one embodiment, a particular data path is identified that has higher than average usage probability based on knowledge of the probabalistic distribution of data values, and the particular data path connecting devices located in the identified higher usage path are modified, such as by shortening the path, so that the path that is known to have a higher usage is made faster. In another embodiment of a device implementing a combinational logic array needing a theoretical plurality of stages for executing the function is implemented with an asynchronous ring including a plurality of connected circuit stages wherein the plurality of stages is a smaller number of stages than the number of the theoretical plurality of stages, control logic for controlling the execution timing of the plurality of stages so that at least one of the plurality of stages executes more than once during the execution of the functi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.