Random access memory having selective intra-bank fast activation of sense amplifiers
US5671188A · kind A · utility
26Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1996 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Jun 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) (10) is disclosed. Memory cell arrays (12) within the DRAM have word lines and bit lines, the bit lines being logically divided into bit line sections (26a-p). Corresponding to each bit line section (26a-p) is a sense/decode section (28a-p) having a fast and slow sense mode of operation. When data are read from a particular bit line section (26a-p) the corresponding sense decode section (28a-p) operates in the fast sense mode while the remaining sense/decode sections (28a-p) operate in the slow sense mode, providing for lower power consumption and/or faster access speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.