I/O system for reducing main processor overhead in initiating I/O requests and servicing I/O completion events
US5671365A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1995 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Oct 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and associated methods for improving I/O performance in a computing system which includes one or more MPUs and one or more IOPs. I/O requests are queued by a requesting MPU in a memory shared with one or more IOPs. Each IOP is associated with a queue. Each IOP may continue processing queued I/O requests after completing processing on an earlier request. In addition, each MPU is associated with a queue shared with the IOPs. When an IOP completes processing of an I/O request, a completion message is added to the requesting MPU's queue and an interrupt is generated for that MPU. The MPU services all completion messages in its queue when the interrupt is processed. A threshold value is associated with each MPU queue. The threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the MPU. The threshold value for each MPU may be tuned to permit the computing system to balance the need for rapid I/O response time with the need for reduced interrupt overhead processing in the MPU. Various physical embodiments of the invention are disclosed wherein the queue is located in either a shared memory or in a register file.…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.