Semiconductor device
US5672894A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1995 |
| Grant date | Sep 30, 1997 |
| Priority date | — |
| Expiry date | Oct 19, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The resistance to electromigration in a double-layer Al wiring structure of lateral DMOS or the like is improved by further reducing ON resistance and mitigating current concentration. The first-layer source wiring and the first-layer drain wiring which are electrically connected to a plurality of source cells and drain cells respectively are formed into a pectinate pattern respectively. The second-layer source wiring and the second-layer drain wiring are also formed into a pectinate pattern respectively and disposed in inclination at 45 degrees to the patterns of the first-layer source wiring and first-layer drain wiring. At the intersections of the first-layer source wiring and the second-layer source wiring, at the intersections of the first-layer drain wiring and the second-layer drain wiring, at the outer circumferential portions of the pectinate patterns of first-layer source and drain wirings and at the source and drain pads, contact holes are provided on a layer insulation film to make a contact between the first-layer source and drain wirings and the second-layer source and drain wirings, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.