Column-to-column isolation in fed display
US5672933A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1995 |
| Grant date | Sep 30, 1997 |
| Priority date | — |
| Expiry date | Oct 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J1/3042
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electron emitter plate (10, 10') for an FED image display has a gate conductive layer (22) spaced by a dielectric insulating layer (25) from a cathode conductive layer formed into a mesh (18). Arrays (12) of microtips (14) are located within mesh spacings (16) for field emission of electrons toward a phosphor layer (34) of an anode plate (11). Cathode layer (18) is patterned into column stripes (19) separated by gaps (17). Gate layer (22) is patterned into row cross-stripes (24) separated by gaps (23) which intersect with stripes (19) at matrix addressable pixel locations (30). Resistive layer (15) is patterned into stripes (40) separated by gaps (42) which interrupt column-to-column electrical communication through resistive layer (15). Unetched strips (43) are provided to bridge gap discontinuities for deposition of gate layer (22) at crossovers of rows (24) between columns (19). In one embodiment, gate layer (22) has a mesh pattern with apertured pads (46) commonly connected along resistive gap edges by marginal buses (50) formed on borders (49) of resistive layer (15) along gaps (42). Adjacent marginal buses (50) are connected by crossover buses (52) formed over bridging str…
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