Circuit and method for reading a memory cell that can store multiple bits of data
US5673221A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1996 |
| Grant date | Sep 30, 1997 |
| Priority date | — |
| Expiry date | Jan 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5632
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.