Integrated circuit memory with multiplexed redundant column data path
US5673227A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1996 |
| Grant date | Sep 30, 1997 |
| Priority date | — |
| Expiry date | May 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory (10) has a redundant column (20) located approximately in the middle a memory array (80, 81). Input/output (I/O) blocks (49, 70) are located on a periphery of the memory (10). A redundant multiplexer (24) is coupled to the redundant column (20) and to a top redundant global data line (36) and a bottom redundant global data line (34). Data is routed between the redundant columns (20) and the I/O blocks (49, 70) via the top and bottom redundant global data lines (36, 34) to effectively shorten the redundant global data line, thereby reducing the amount of redundant data line load capacitance. A fuse circuit (50) is used to program which of the top or bottom global data lines (36, 34) replaces a defective data path. This arrangement permits increased redundant array efficiency while achieving the required performance goals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.