Processor structure and method for renamable trap-stack
US5673408A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Sep 30, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor and associated method for taking and returning from traps speculatively. The data processor supports a predefined number of trap levels for taking nested traps each having a corresponding trap level. The data processor comprises means to form checkpoints, means to back up to the checkpoints, means to take a trap, means to return from a trap, registers, and a trap stack unit. The registers have contents that define the state of the data processor each time a trap is taken. The trap stack unit includes a trap stack data storage structure that has a greater number of trap slack storage entries than there are trap levels. It also includes a freelist unit that maintains a current availability list of the trap stack storage entries that are currently available for mapping to one of the trap levels. The freelist unit identifies, each time a trap is taken, a next one of the currently available trap stack storage entries for mapping to the corresponding one of the trap levels. The trap stack unit further includes read/write logic that writes, for each trap taken, the contents of the registers to the next one of the currently available trap stack storage entries. It still fu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.