Parity bit emulator with write parity bit checking
US5673419A · kind A · utility
9Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 19, 1995 |
| Grant date | Sep 30, 1997 |
| Priority date | — |
| Expiry date | May 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a parity bit emulator circuit which generates a parity bit to be associated with a data byte output by a signal in-line memory module (SIMM) to a CPU. Each parity bit emulator monitors four consecutive write cycles to determine whether the system parity is even or odd, and thereafter monitors each write cycle to determine if a data transfer error has occurred during a write from the CPU to the SIMM. A state machine circuit provides appropriate timing for write and read cycle memory access protocols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.