Circuit with sleep mode having counter
US5675282A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 1995 |
| Grant date | Oct 7, 1997 |
| Priority date | — |
| Expiry date | Aug 9, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit has a plurality of circuit elements, each of which is equipped with a power saving device for conserving power. This offers design flexibility to more easily change the number of circuit elements in the integrated circuit. Each circuit element detects the input data with the aid of an input detector circuit. The input detector triggers a timer circuit to measure the time required for the circuit element to process the data. The timer circuit turns on an action flag at the start of the process, and turns off the action flag at the end of the process. When the action flag is on, a switch circuit provides either a clock signal or the power to a main circuit. This allows the main circuit to enter an activation mode. When the action flag is off, the switch circuit either provides a low-speed clock signal or suspends the supply of the clock signal or the power to the main circuit. This allows the main circuit to enter a sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.