Method and apparatus for efficient addressing of DRAM in a video decompression processor
US5675387A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1996 |
| Grant date | Oct 7, 1997 |
| Priority date | — |
| Expiry date | Jul 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Pixel data is stored and subsequently read from a random access memory of a video decompression processor in a manner that reduces the number of times different rows of the RAM must be addressed in order to retrieve portions of the pixel data therefrom. Pixel data from a video frame is stored in the RAM as a plurality of pages. Each page substantially fills a different row of the RAM and corresponds to a different section of the video frame. A motion vector is decoded to determine the location of a prediction area within the video frame. In the event that the prediction area encompasses more than one of the pages of the video frame, the pixel data is retrieved one page at a time, minimizing the number of row changes required when addressing the RAM to retrieve the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.