Integrated semiconductor memory device
US5675543A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 1996 |
| Grant date | Oct 7, 1997 |
| Priority date | — |
| Expiry date | Aug 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated semiconductor memory device having a semiconductor substrate with a redundant circuit arrangement formed thereon for replacing a defective memory cell of the integrated semiconductor memory device by selecting a redundant memory cell likewise disposed on the semiconductor substrate, the memory cells of the integrated semiconductor memory device being constructed and addressable in blocks; the redundant memory cells being combined into a redundant memory cell field addressable as a unit by the redundant circuit arrangement; and the redundant circuit arrangement having a redundant selection circuit for selecting a redundant memory cell from the redundant memory cell field to replace a defective memory cell from any of the memory cell blocks, includes a redundance control circuit forming part of the redundant circuit arrangement and enabling, as a function of a programmed redundant selection signal, one of the data content of a normal memory cell and the data content of a redundant memory cell suitably substituted in the event of a defect in the normal memory cell of the redundant memory cell field, the redundance control circuit being connected downstream from read amplifi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.