Interrupt message delivery identified by storage location of received interrupt data

US5675807A · kind A · utility

Assignee

• Tandem Computers Incorporated · US

Inventors

• Geoffrey Ignatius Iswandhi · Sunnyvale, US
• William E. Baker · Austin, US
• William P. Bunton · Pflugerville, US
• John Coddington · Austin, US
• Daniel L. Fowler · Kentwood, US
• David J. Garcia · Los Gatos, US
• Paul N. Hintikka · Austin, US
• Susan S. Meredith · Hillsboro, US
• Stephen H. Miller · Naples, US
• David P. Sonnier · Austin, US
• William J. Watson · Austin, US
• Frank A. Williams · Austin, US

Key dates

• Filing date: Jun 7, 1995
• Grant date: Oct 7, 1997
• Expiry date: Jun 7, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L12/56
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.