Mask for forming features on a semiconductor substrate and a method for forming the mask
US5676853A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 1996 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | May 21, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/945
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mask and a method for forming a mask on a surface of an underlying layer of material used in semiconductor device manufacturing. The mask is a mixture of mask particles and spacer particles. The spacer particles space the mask particles apart from one another to control the distance and the uniformity of the distribution of mask particles across the surface of the underlying layer. The spacer particles and mask particles have different physical properties that allow the spacer particles to be selectively removed from the surface of the underlying layer. The spacer particles are preferably removed from the surface of the underlying layer by selectively etching the spacer particles from the underlying layer. After the spacer particles are removed from the underlying layer, the mask particles remain on the underlying layer to provide spaced apart mask elements on the surface of the underlying layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.