Shallow trench isolation in integrated circuits
US5677564A · kind A · utility
4Cited by
10References
5Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Aug 21, 1996 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | Aug 21, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/763
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention concerns fabrication of oxide-filled isolation trenches in integrated circuits. The invention etches a network of trenches in the surface of a uniformly doped wafer which has experienced no substantial processing steps. Such a wafer will have little, if any, surface damage. Such a wafer will etch to the same depth everywhere, because two major factors which affect etching rate are (a) surface damage and (b) doping non-uniformity, and these factors are absent. The trenches are then filled with oxide. They define islands upon which devices (such as transistors) may now be fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.