Semiconductor multi-package stack
US5677569A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1995 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | Oct 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor multi-package including a plurality of individual semiconductor chip packages stacked over one another. The individual packages have a substrate provided with a plurality of bonding pads, electrode pads electrically connected to the bonding pads through wires, and chips attached to upper and lower surfaces of the substrate. A paddles lead frame is provided onto which the individual packages are attached to upper and lower surfaces thereof, and variants thereof. For these packages, since individual packages are mounted on upper and lower surfaces of a single printed circuit board or lead frame, the mounting density can be significantly increased and their production can be simplified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.