Chip sized semiconductor device
US5677576A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 1996 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | Mar 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00013
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip sized semiconductor device includes a semiconductor chip having upper and lower surfaces. The chip has electrodes formed on the upper surface thereof. An electrically insulating passivation film is formed on the upper surface of the semiconductor chip, except for areas where the electrodes exist. An anisotropic conductive sheet has an upper surface providing with a circuit pattern formed thereon and a second surface being adhered to the passivation film. The circuit pattern has inner and outer connecting portions. The electrically insulating film covers the upper surface of the anisotropic conductive sheet so that the outer connecting portions of the circuit pattern are exposed to be connected to external connecting terminals. The anisotropic conductive sheet is partially pressed at positions correspond to the electrodes, so that the inner portions of the circuit pattern are electrically connected to said electrodes of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.