Faulty operation prevention circuit of a computer
US5677838A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1995 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | Apr 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldTransport
- WIPO sectorMechanical engineering
Abstract
A computer (CPU) applied a faulty operation prevention circuit outputs a pulse signal having a predetermined period during normal operation. If the computer does not output the pulse signal during the predetermined period, a AND gate in the faulty operation prevention circuit shuts off a control signal output from the computer which can ignite a squib in a vehicular occupant protecting system because the computer is not working. The AND gate keeps shutting off the control signal until the computer outputs the pulse signal. Therefore, the faulty operation prevention circuit prevents the squib from being ignited based on a faulty operation of the computer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.