Methods of programming flash EEPROM integrated circuit memory devices to prevent inadvertent programming of nondesignated NAND memory cells therein
US5677873A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1996 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | Sep 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of programming flash EEPROM integrated circuit memory devices containing an array of NAND cells therein include the steps of applying a preselected logic signal to a select transistor of a NAND memory cell to inhibit the likelihood of inadvertent programming thereof when adjacent cells are being programmed. According to one embodiment, a first logic signal having a first non-zero potential (V.sub.fp) is applied to a bit line BL of a first NAND memory cell in the array. Then, at commencement of a first time interval (TI), a second logic signal having a second potential which is greater than the first potential is applied to the gate (SSL) of the first select transistor ST1 to thereby turn-on the first select transistor "hard" and drive the potential of a source (S) thereof towards the potential of the bit line (i.e., V.sub.fp). Here, the first potential V.sub.fp is preferably selected to be higher than the power supply voltage VCC. Then, upon termination of the first time interval TI, the potential of the second bilevel logic signal is reduced from the second potential to the first potential V.sub.fp (or ground GND) to thereby limit conduction across the channel of the first…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.