Method of optimizing the execution of program instuctions by an emulator using a plurality of execution units
US5678032A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1995 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | Sep 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45504
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An application such as an interpretative emulator executes a wide range of different classes of emulated program instructions developed for the processor architecture being emulated on a host system which includes an dual integer pipelined execution unit. The sets of RISC instructions which execute emulated program instructions are organized within the emulator so as to be processed as two distinct instruction streams by the dual integer pipelined execution units wherein one of the pipelined unit performs the steps necessary to completing a current or foreground like operation on each emulated program instruction while the other pipelined unit performs the steps of an anticipated lookahead or background like operation on the next emulated program instruction. By having one unit execute operations such as interpreting each program instruction within an established foreground instruction stream and the other unit execute operations such as prefetching each next program instruction within an established background instruction stream, the speed of emulated program execution is optimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.